Device analog input pin, register and interrupt vector assignments of phase current feedback signal(s) More...

Collaboration diagram for Microcontroller Abstraction:

#define	_BUCK_ISNS1_ADCInterrupt _ADCAN1Interrupt
	ADC input assignments of phase current feedback signals. More...

#define	_BUCK_ISNS1_ADCISR_IF _ADCAN1IF

#define	BUCK_ISNS1_ANSEL _ANSELA1
	GPIO analog function mode enable bit. More...

#define	BUCK_ISNS1_ADCCORE 1
	0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core More...

#define	BUCK_ISNS1_ADCIN 1
	Analog input number (e.g. '5' for 'AN5') More...

#define	BUCK_ISNS1_ADCBUF ADCBUF1
	ADC input buffer of this ADC channel. More...

#define	BUCK_ISNS1_ADCTRIG PG2TRIGB
	Register used for trigger placement. More...

#define	BUCK_ISNS1_TRGSRC BUCK_PWM1_TRGSRC_TRG2
	PWM1 (=PG2) Trigger 2 via PGxTRIGB. More...

#define	_BUCK_ISNS2_ADCInterrupt _ADCAN4Interrupt

#define	_BUCK_ISNS2_ADCISR_IF _ADCAN4IF

#define	BUCK_ISNS2_ANSEL _ANSELA4
	GPIO analog function mode enable bit. More...

#define	BUCK_ISNS2_ADCCORE 8
	0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core More...

#define	BUCK_ISNS2_ADCIN 4
	Analog input number (e.g. '5' for 'AN5') More...

#define	BUCK_ISNS2_ADCBUF ADCBUF4
	ADC input buffer of this ADC channel. More...

#define	BUCK_ISNS2_ADCTRIG PG4TRIGB
	Register used for trigger placement. More...

#define	BUCK_ISNS2_TRGSRC BUCK_PWM2_TRGSRC_TRG2
	PWM2 (=PG4) Trigger 2 via PGxTRIGB. More...

Detailed Description

Device analog input pin, register and interrupt vector assignments of phase current feedback signal(s)

Macro Definition Documentation

◆ _BUCK_ISNS1_ADCInterrupt

#define _BUCK_ISNS1_ADCInterrupt _ADCAN1Interrupt

ADC input assignments of phase current feedback signals.

In this section the ADC input channels, related ADC result buffers, trigger sources and interrupt vectors are defined. These settings allow the fast re-assignments of feedback signals in case of hardware changes.

Definition at line 623 of file epc9143_r40_hwdescr.h.

◆ _BUCK_ISNS1_ADCISR_IF

#define _BUCK_ISNS1_ADCISR_IF _ADCAN1IF

Definition at line 624 of file epc9143_r40_hwdescr.h.

◆ _BUCK_ISNS2_ADCInterrupt

#define _BUCK_ISNS2_ADCInterrupt _ADCAN4Interrupt

Definition at line 633 of file epc9143_r40_hwdescr.h.

◆ _BUCK_ISNS2_ADCISR_IF

#define _BUCK_ISNS2_ADCISR_IF _ADCAN4IF

Definition at line 634 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_ADCBUF

#define BUCK_ISNS1_ADCBUF ADCBUF1

ADC input buffer of this ADC channel.

Definition at line 629 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_ADCCORE

#define BUCK_ISNS1_ADCCORE 1

0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core

Definition at line 627 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_ADCIN

#define BUCK_ISNS1_ADCIN 1

Analog input number (e.g. '5' for 'AN5')

Definition at line 628 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_ADCTRIG

#define BUCK_ISNS1_ADCTRIG PG2TRIGB

Register used for trigger placement.

Definition at line 630 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_ANSEL

#define BUCK_ISNS1_ANSEL _ANSELA1

GPIO analog function mode enable bit.

Definition at line 626 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS1_TRGSRC

#define BUCK_ISNS1_TRGSRC BUCK_PWM1_TRGSRC_TRG2

PWM1 (=PG2) Trigger 2 via PGxTRIGB.

Definition at line 631 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_ADCBUF

#define BUCK_ISNS2_ADCBUF ADCBUF4

ADC input buffer of this ADC channel.

Definition at line 639 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_ADCCORE

#define BUCK_ISNS2_ADCCORE 8

0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core

Definition at line 637 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_ADCIN

#define BUCK_ISNS2_ADCIN 4

Analog input number (e.g. '5' for 'AN5')

Definition at line 638 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_ADCTRIG

#define BUCK_ISNS2_ADCTRIG PG4TRIGB

Register used for trigger placement.

Definition at line 640 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_ANSEL

#define BUCK_ISNS2_ANSEL _ANSELA4

GPIO analog function mode enable bit.

Definition at line 636 of file epc9143_r40_hwdescr.h.

◆ BUCK_ISNS2_TRGSRC

#define BUCK_ISNS2_TRGSRC BUCK_PWM2_TRGSRC_TRG2

PWM2 (=PG4) Trigger 2 via PGxTRIGB.

Definition at line 641 of file epc9143_r40_hwdescr.h.