Collaboration diagram for Converter Phase #2:

#define	BUCK_PWM2_CHANNEL 4U
	PWM peripheral output pins, control signals and register assignments of converter phase #2. More...

#define	BUCK_PWM2_GPIO_INSTANCE 1U
	Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc. More...

#define	BUCK_PWM2_GPIO_PORT_PINH 9U
	Port Pin Number. More...

#define	BUCK_PWM2_GPIO_PORT_PINL 8U
	Port Pin Number. More...

#define	BUCK_PWM2_PDC PG4DC
	PWM Instance Duty Cycle Register. More...

#define	BUCK_PWM2H_TRIS _TRISB9
	Device Port TRIS register. More...

#define	BUCK_PWM2H_WR _LATB9
	Device Pin WRITE. More...

#define	BUCK_PWM2H_RD _RB9
	Device Pin READ. More...

#define	BUCK_PWM2H_RPx (uint8_t)41
	Device Pin output remappable pin number (RPx) More...

#define	BUCK_PWM2H_INIT { _LATB9 = 0; _TRISB9 = 0; }

#define	BUCK_PWM2L_TRIS _TRISB8
	Device Port TRIS register. More...

#define	BUCK_PWM2L_WR _LATB8
	Device Pin WRITE. More...

#define	BUCK_PWM2L_RD _RB8
	Device Pin READ. More...

#define	BUCK_PWM2L_RPx (uint8_t)40
	Device Pin output remappable pin number (RPx) More...

#define	BUCK_PWM2L_INIT { _LATB8 = 0; _TRISB8 = 0; }

#define	_BUCK_PWM2_Interrupt _PWM4Interrupt
	PWM Interrupt Serivice Routine label. More...

#define	BUCK_PWM2_IF _PWM4IF
	PWM Interrupt Flag Bit. More...

#define	BUCK_PWM2_IE _PWM4IE
	PWM Interrupt Enable Bit. More...

#define	BUCK_PWM2_IP _PWM4IP
	PWM Interrupt Priority. More...

#define	BUCK_PWM2_TRGSRC_TRG1 0b01010
	PWM2 Trigger #1 Trigger Source of this channel. More...

#define	BUCK_PWM2_TRGSRC_TRG2 0b01011
	PWM2 Trigger #2 Trigger Source of this channel. More...

#define	BUCK_PWM2_PGxTRIGA PG4TRIGA
	PWM2 trigger register A. More...

#define	BUCK_PWM2_PGxTRIGB PG4TRIGB
	PWM2 trigger register B. More...

#define	BUCK_PWM2_PGxTRIGC PG4TRIGC
	PWM2 trigger register C. More...

#define	BUCK_PWM2_ADTR1OFS 0
	ADC Trigger 1 Offset: 0...31. More...

#define	BUCK_PWM2_ADTR1PS 0
	ADC Trigger 1 Postscaler: 0...31. More...

#define	BUCK_PWM2_UPDREQ PG1STATbits.UPDREQ

Detailed Description

Macro Definition Documentation

◆ _BUCK_PWM2_Interrupt

#define _BUCK_PWM2_Interrupt _PWM4Interrupt

PWM Interrupt Serivice Routine label.

Definition at line 350 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_ADTR1OFS

#define BUCK_PWM2_ADTR1OFS 0

ADC Trigger 1 Offset: 0...31.

Definition at line 360 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_ADTR1PS

#define BUCK_PWM2_ADTR1PS 0

ADC Trigger 1 Postscaler: 0...31.

Definition at line 361 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_CHANNEL

#define BUCK_PWM2_CHANNEL 4U

PWM peripheral output pins, control signals and register assignments of converter phase #2.

Converter phase #2 uses a simple half-bridge to commutate the switch node. The signal source therefore only requires a single PWM generator instance to be configured in fixed frequency complementary mode with dead times. Additional PWM peripheral features are used by the firmware to respond to interrupts, trigger ADC conversions, control device output pins during startup and fault responses and to change timing settings on the fly.

Please review the device data sheet for details about register names and settings. PWM Instance Index (e.g. 1=PWM1, 2=PWM2, etc.)

Definition at line 331 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_GPIO_INSTANCE

#define BUCK_PWM2_GPIO_INSTANCE 1U

Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc.

Definition at line 332 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_GPIO_PORT_PINH

#define BUCK_PWM2_GPIO_PORT_PINH 9U

Port Pin Number.

Definition at line 333 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_GPIO_PORT_PINL

#define BUCK_PWM2_GPIO_PORT_PINL 8U

Port Pin Number.

Definition at line 334 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_IE

#define BUCK_PWM2_IE _PWM4IE

PWM Interrupt Enable Bit.

Definition at line 352 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_IF

#define BUCK_PWM2_IF _PWM4IF

PWM Interrupt Flag Bit.

Definition at line 351 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_IP

#define BUCK_PWM2_IP _PWM4IP

PWM Interrupt Priority.

Definition at line 353 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_PDC

#define BUCK_PWM2_PDC PG4DC

PWM Instance Duty Cycle Register.

Definition at line 336 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_PGxTRIGA

#define BUCK_PWM2_PGxTRIGA PG4TRIGA

PWM2 trigger register A.

Definition at line 356 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_PGxTRIGB

#define BUCK_PWM2_PGxTRIGB PG4TRIGB

PWM2 trigger register B.

Definition at line 357 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_PGxTRIGC

#define BUCK_PWM2_PGxTRIGC PG4TRIGC

PWM2 trigger register C.

Definition at line 358 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_TRGSRC_TRG1

#define BUCK_PWM2_TRGSRC_TRG1 0b01010

PWM2 Trigger #1 Trigger Source of this channel.

Definition at line 354 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_TRGSRC_TRG2

#define BUCK_PWM2_TRGSRC_TRG2 0b01011

PWM2 Trigger #2 Trigger Source of this channel.

Definition at line 355 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2_UPDREQ

#define BUCK_PWM2_UPDREQ PG1STATbits.UPDREQ

Definition at line 363 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2H_INIT

#define BUCK_PWM2H_INIT { _LATB9 = 0; _TRISB9 = 0; }

Definition at line 342 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2H_RD

#define BUCK_PWM2H_RD _RB9

Device Pin READ.

Definition at line 340 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2H_RPx

#define BUCK_PWM2H_RPx (uint8_t)41

Device Pin output remappable pin number (RPx)

Definition at line 341 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2H_TRIS

#define BUCK_PWM2H_TRIS _TRISB9

Device Port TRIS register.

Definition at line 338 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2H_WR

#define BUCK_PWM2H_WR _LATB9

Device Pin WRITE.

Definition at line 339 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2L_INIT

#define BUCK_PWM2L_INIT { _LATB8 = 0; _TRISB8 = 0; }

Definition at line 348 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2L_RD

#define BUCK_PWM2L_RD _RB8

Device Pin READ.

Definition at line 346 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2L_RPx

#define BUCK_PWM2L_RPx (uint8_t)40

Device Pin output remappable pin number (RPx)

Definition at line 347 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2L_TRIS

#define BUCK_PWM2L_TRIS _TRISB8

Device Port TRIS register.

Definition at line 344 of file epc9143_r40_hwdescr.h.

◆ BUCK_PWM2L_WR

#define BUCK_PWM2L_WR _LATB8

Device Pin WRITE.

Definition at line 345 of file epc9143_r40_hwdescr.h.