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EPC9143 300 W 16th Brick DC/DC Module Reference Design
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EPC9143 300 W 16th Brick DC/DC Module Reference Design
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Collaboration diagram for Converter Phase #1:| #define | BUCK_PWM1_CHANNEL 2U |
| PWM peripheral output pins, control signals and register assignments of converter phase #1. More... | |
| #define | BUCK_PWM1_GPIO_INSTANCE 1U |
| Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc. More... | |
| #define | BUCK_PWM1_GPIO_PORT_PINH 12U |
| Port Pin Number. More... | |
| #define | BUCK_PWM1_GPIO_PORT_PINL 13U |
| Port Pin Number. More... | |
| #define | BUCK_PWM1_PDC PG2DC |
| PWM Instance Duty Cycle Register. More... | |
| #define | BUCK_PWM1H_TRIS _TRISB12 |
| Device Port TRIS register. More... | |
| #define | BUCK_PWM1H_WR _LATB12 |
| Device Pin WRITE. More... | |
| #define | BUCK_PWM1H_RD _RB12 |
| Device Pin READ. More... | |
| #define | BUCK_PWM1H_RPx (uint8_t)44 |
| Device Pin output remappable pin number (RPx) More... | |
| #define | BUCK_PWM1L_TRIS _TRISB13 |
| Device Port TRIS register. More... | |
| #define | BUCK_PWM1L_WR _LATB13 |
| Device Pin WRITE. More... | |
| #define | BUCK_PWM1L_RD _RB13 |
| Device Pin READ. More... | |
| #define | BUCK_PWM1L_RPx (uint8_t)45 |
| Device Pin output remappable pin number (RPx) More... | |
| #define | _BUCK_PWM1_Interrupt _PWM2Interrupt |
| PWM Interrupt Service Routine label. More... | |
| #define | BUCK_PWM1_IF _PWM2IF |
| PWM Interrupt Flag Bit. More... | |
| #define | BUCK_PWM1_IE _PWM2IE |
| PWM Interrupt Enable Bit. More... | |
| #define | BUCK_PWM1_IP _PWM2IP |
| PWM Interrupt Priority. More... | |
| #define | BUCK_PWM1_TRGSRC_TRG1 0b00110 |
| PWM Trigger #1 Trigger Source of this channel. More... | |
| #define | BUCK_PWM1_TRGSRC_TRG2 0b00111 |
| PWM Trigger #2 Trigger Source of this channel. More... | |
| #define | BUCK_PWM1_PGxTRIGA PG2TRIGA |
| PWM trigger register A. More... | |
| #define | BUCK_PWM1_PGxTRIGB PG2TRIGB |
| PWM trigger register B. More... | |
| #define | BUCK_PWM1_PGxTRIGC PG2TRIGC |
| PWM trigger register C. More... | |
| #define | BUCK_PWM1_ADTR1OFS 0U |
| ADC Trigger 1 Offset: 0...31. More... | |
| #define | BUCK_PWM1_ADTR1PS 0U |
| ADC Trigger 1 Postscaler: 0...31. More... | |
| #define | BUCK_PWM1_UPDREQ PG1STATbits.UPDREQ |
| #define _BUCK_PWM1_Interrupt _PWM2Interrupt |
PWM Interrupt Service Routine label.
Definition at line 298 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_ADTR1OFS 0U |
ADC Trigger 1 Offset: 0...31.
Definition at line 308 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_ADTR1PS 0U |
ADC Trigger 1 Postscaler: 0...31.
Definition at line 309 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_CHANNEL 2U |
PWM peripheral output pins, control signals and register assignments of converter phase #1.
Converter phase #1 uses a simple half-bridge to commutate the switch node. The signal source therefore only requires a single PWM generator instance to be configured in fixed frequency complementary mode with dead times. Additional PWM peripheral features are used by the firmware to respond to interrupts, trigger ADC conversions, control device output pins during startup and fault responses and to change timing settings on the fly.
Please review the device data sheet for details about register names and settings. PWM Instance Index (e.g. 1=PWM1, 2=PWM2, etc.)
Definition at line 283 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_GPIO_INSTANCE 1U |
Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc.
Definition at line 284 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_GPIO_PORT_PINH 12U |
Port Pin Number.
Definition at line 285 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_GPIO_PORT_PINL 13U |
Port Pin Number.
Definition at line 286 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_IE _PWM2IE |
PWM Interrupt Enable Bit.
Definition at line 300 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_IF _PWM2IF |
PWM Interrupt Flag Bit.
Definition at line 299 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_IP _PWM2IP |
PWM Interrupt Priority.
Definition at line 301 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_PDC PG2DC |
PWM Instance Duty Cycle Register.
Definition at line 288 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_PGxTRIGA PG2TRIGA |
PWM trigger register A.
Definition at line 304 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_PGxTRIGB PG2TRIGB |
PWM trigger register B.
Definition at line 305 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_PGxTRIGC PG2TRIGC |
PWM trigger register C.
Definition at line 306 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_TRGSRC_TRG1 0b00110 |
PWM Trigger #1 Trigger Source of this channel.
Definition at line 302 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_TRGSRC_TRG2 0b00111 |
PWM Trigger #2 Trigger Source of this channel.
Definition at line 303 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1_UPDREQ PG1STATbits.UPDREQ |
Definition at line 311 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1H_RD _RB12 |
Device Pin READ.
Definition at line 291 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1H_RPx (uint8_t)44 |
Device Pin output remappable pin number (RPx)
Definition at line 292 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1H_TRIS _TRISB12 |
Device Port TRIS register.
Definition at line 289 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1H_WR _LATB12 |
Device Pin WRITE.
Definition at line 290 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1L_RD _RB13 |
Device Pin READ.
Definition at line 295 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1L_RPx (uint8_t)45 |
Device Pin output remappable pin number (RPx)
Definition at line 296 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1L_TRIS _TRISB13 |
Device Port TRIS register.
Definition at line 293 of file epc9143_r40_hwdescr.h.
| #define BUCK_PWM1L_WR _LATB13 |
Device Pin WRITE.
Definition at line 294 of file epc9143_r40_hwdescr.h.