 |
EPC9143 300 W 16th Brick DC/DC Module Reference Design
|
|
|
EPC9143 300 W 16th Brick DC/DC Module Reference Design
|
|
User-declaration of startup timing periods using physical quantities. More...
Collaboration diagram for User Settings:| #define | BUCK_POWER_ON_DELAY (float) 200e-3 |
| Global defines for soft-start specific parameters. More... | |
| #define | BUCK_VRAMP_PERIOD (float) 100e-3 |
| voltage ramp-up period in [sec] More... | |
| #define | BUCK_IRAMP_PERIOD (float) 100e-3 |
| output current ramp-up period in [sec] More... | |
| #define | BUCK_POWER_GOOD_DELAY (float) 200e-3 |
| power good delay in [sec] More... | |
User-declaration of startup timing periods using physical quantities.
| #define BUCK_IRAMP_PERIOD (float) 100e-3 |
output current ramp-up period in [sec]
Definition at line 713 of file epc9143_r40_hwdescr.h.
| #define BUCK_POWER_GOOD_DELAY (float) 200e-3 |
power good delay in [sec]
Definition at line 714 of file epc9143_r40_hwdescr.h.
| #define BUCK_POWER_ON_DELAY (float) 200e-3 |
Global defines for soft-start specific parameters.
This section is used to define power supply startup timing settings. The soft-start sequence is part of the power controller. It allows to program specific timings for
After the startup has passed these three timing periods, the power supply is ending up in "normal" operation, continuously regulating the output until a fault is detected or the operating state is changed for any other reason. When the output voltage reference is changed, the power control state machine will use the voltage ramp slope defined here to tune from the recent voltage reference to the new reference value. During this period the BUSY-bit of the power controller (status word, bit #7) will be set. This status bit will be cleared automatically by the power controller state machine once the new reference value has been applied and the converter is back in constant regulation mode.
Pre-compiler macros are used to translate physical values into binary (integer) numbers to be written to SFRs and variables.
(see Conversion Macros for details)
Please Note:
On EPC9143 Rev 4 it takes roughly 50 ms until the auxiliary power has been started and the controller completes self-test and peripheral configuration. After this period the controller starts to execute the power control state machine.
This additional startup delay of ~50 ms is not considered here and needs to be taken into account when adjusting startup timing. power on delay in [sec]
Definition at line 711 of file epc9143_r40_hwdescr.h.
| #define BUCK_VRAMP_PERIOD (float) 100e-3 |
voltage ramp-up period in [sec]
Definition at line 712 of file epc9143_r40_hwdescr.h.