EPC9143 300 W 16th Brick DC/DC Module Reference Design
config_bits.c
1 /*
2  * File: config_bits.c
3  * Author: M91406
4  *
5  * Created on July 8, 2019, 2:39 PM
6  */
7 
8 
9 #include <xc.h>
10 #include "config/hal.h"
11 
12 // Configuration bits: selected in the GUI
13 
14 
15 // FICD
16 
17 #pragma config ICS = PGD3 //ICD Communication Channel Select bits->Communicate on PGC2 and PGD2
18 #pragma config JTAGEN = OFF //JTAG Enable bit->JTAG is disabled
19 
20 
21 // FALTREG
22 
23 #if (_OSTIMER_PRIORITY == 0)
24  #pragma config CTXT1 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
25 #elif (_OSTIMER_PRIORITY == 1)
26  #pragma config CTXT1 = IPL1 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
27 #elif (_OSTIMER_PRIORITY == 2)
28  #pragma config CTXT1 = IPL2 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
29 #elif (_OSTIMER_PRIORITY == 3)
30  #pragma config CTXT1 = IPL3 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
31 #elif (_OSTIMER_PRIORITY == 4)
32  #pragma config CTXT1 = IPL4 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
33 #elif (_OSTIMER_PRIORITY == 5)
34  #pragma config CTXT1 = IPL5 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
35 #elif (_OSTIMER_PRIORITY == 6)
36  #pragma config CTXT1 = IPL6 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
37 #else
38  #pragma config CTXT1 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
39  #pragma message "WARNING: operating system timer priority invalid."
40 #endif
41 
42 #if (BUCK_VOUT_ISR_PRIORITY == 0)
43  #pragma config CTXT2 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
44 #elif (BUCK_VOUT_ISR_PRIORITY == 1)
45  #pragma config CTXT2 = IPL1 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
46 #elif (BUCK_VOUT_ISR_PRIORITY == 2)
47  #pragma config CTXT1 = IPL2 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
48 #elif (BUCK_VOUT_ISR_PRIORITY == 3)
49  #pragma config CTXT2 = IPL3 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
50 #elif (BUCK_VOUT_ISR_PRIORITY == 4)
51  #pragma config CTXT2 = IPL4 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
52 #elif (BUCK_VOUT_ISR_PRIORITY == 5)
53  #pragma config CTXT2 = IPL5 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
54 #elif (BUCK_VOUT_ISR_PRIORITY == 6)
55  #pragma config CTXT2 = IPL6 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
56 #else
57  #pragma config CTXT2 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
58  #pragma message "WARNING: buck converter output voltage loop control interrupt priority invalid."
59 #endif
60 
61 #pragma config CTXT3 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits
62 #pragma config CTXT4 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits
63 
64 
65 // FSEC
66 #pragma config BWRP = OFF //Boot Segment Write-Protect bit->Boot Segment may be written
67 #pragma config BSS = DISABLED //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
68 #pragma config BSEN = OFF //Boot Segment Control bit->No Boot Segment
69 #pragma config GWRP = OFF //General Segment Write-Protect bit->General Segment may be written
70 #pragma config GSS = DISABLED //General Segment Code-Protect Level bits->No Protection (other than GWRP)
71 #pragma config CWRP = OFF //Configuration Segment Write-Protect bit->Configuration Segment may be written
72 #pragma config CSS = DISABLED //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
73 #pragma config AIVTDIS = OFF //Alternate Interrupt Vector Table bit->Disabled AIVT
74 
75 // FBSLIM
76 #pragma config BSLIM = 8191 //Boot Segment Flash Page Address Limit bits->8191
77 
78 // FOSCSEL
79 #pragma config FNOSC = FRCDIVN //Oscillator Source Selection->Fast RC Oscillator with divide-by-N with PLL module (FRCPLL)
80 #pragma config IESO = OFF //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source
81 
82 // FOSC
83 #pragma config POSCMD = NONE //Primary Oscillator Mode Select bits->Primary Oscillator disabled
84 #pragma config OSCIOFNC = ON //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
85 #pragma config FCKSM = CSECMD //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
86 #pragma config PLLKEN = ON //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
87 #pragma config XTCFG = G1 //XT Config->24-32 MHz crystals
88 #pragma config XTBST = DISABLE //XT Boost->Boost the kick-start
89 
90 // FWDT
91 //#pragma config RWDTPS = PS2147483648 //Run Mode Watchdog Timer Post Scaler select bits->1:2147483648
92 #pragma config RCLKSEL = LPRC //Watchdog Timer Clock Select bits->Always use LPRC
93 #pragma config WINDIS = OFF //Watchdog Timer Window Enable bit->Watchdog Timer in Window mode
94 #pragma config WDTWIN = WIN25 //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
95 #pragma config RWDTPS = PS128 //Run Mode Watchdog Timer Post Scaler select bits->1:128
96 #pragma config SWDTPS = PS2147483648 //Sleep Mode Watchdog Timer Post Scaler select bits->1:2147483648
97 #pragma config FWDTEN = ON_SW //Watchdog Timer Enable bit->WDT controlled via SW, use WDTCON.ON bit
98 
99 // FPOR
100 #pragma config BISTDIS = DISABLED //Memory BIST Feature Disable->mBIST on reset feature disabled
101 
102 // FDMTIVTL
103 #pragma config DMTIVTL = 0 //Dead Man Timer Interval low word->0
104 
105 // FDMTIVTH
106 #pragma config DMTIVTH = 0 //Dead Man Timer Interval high word->0
107 
108 // FDMTCNTL
109 #pragma config DMTCNTL = 0 //Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0
110 
111 // FDMTCNTH
112 #pragma config DMTCNTH = 0 //Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0
113 
114 // FDMT
115 #pragma config DMTDIS = OFF //Dead Man Timer Disable bit->Dead Man Timer is Disabled and can be enabled by software
116 
117 // FDEVOPT
118 #pragma config ALTI2C1 = OFF //Alternate I2C1 Pin bit->I2C1 mapped to SDA1/SCL1 pins
119 #pragma config ALTI2C2 = OFF //Alternate I2C2 Pin bit->I2C2 mapped to SDA2/SCL2 pins
120 #pragma config SPI2PIN = PPS //SPI2 Pin Select bit->SPI2 uses I/O remap (PPS) pins
121 #pragma config SMB3EN = SMBUS3 //SM Bus Enable->SMBus 3.0 input levels
122